AN-0988 application note one technology way ? p. o. box 9106 ? norwood, ma 02062-9106, u.s.a. ? tel: 781.329.4700 ? fax: 781.461.3113 ? www.analog.com the ad9552: a programmable crystal oscillator for network clocking applications by ken gentile the ubiquitous quartz crystal oscillator has been the workhorse of timekeeping applications for decades. low cost, coupled with relatively high stability, is the driving force behind the success of the quartz crystal oscillator in a broad range of applications. the high resonant q factor makes the quartz crystal oscillator an attractive candidate for the resonant element in fixed fre- quency oscillators. however, an ever-increasing number of network clock applications require a stable, single frequency oscillator as a source for synthesizing different network frequencies. the ad9552 is a low cost, integrated solution for such applications. rev. 0 | page 1 of 8 phase detector loop filter voltage controlled oscillator feedback divider (n) oscillator f ref f out = n f ref quartz crystal pll 07918-001 figure 1. pll-based frequency upconverter
AN-0988 application note rev. 0 | page 2 of 8 table of contents frequency upconversion ................................................................. 3 ? the ad9552 architecture ............................................................... 4 ? conclusion..........................................................................................8 ?
application note AN-0988 rev. 0 | page 3 of 8 frequency upconversion the relatively low resonant frequency of a quartz crystal resonator (typically less than 50 mhz for fundamental mode resonance) is a shortcoming for network applications requiring an output frequency in excess of 100 mhz. the higher output frequency requirement of these applications implies the need for translating the relatively low output frequency of the basic crystal oscillator to a higher frequency, a process often referred to as upconversion. one of the most common upconversion methods involves the use a phase-locked loop (pll) with a frequency divider in its feedback path (see figure 1 ). the output frequency (f o ) is given by f o = n f ref where: n is the frequency divider value. f ref is the input frequency. generally, the bandwidth of the loop filter is relatively narrow in order to minimize spurious artifacts in the output spectrum. furthermore, by making n programmable, the pll upconverter solves the problem of producing different output frequencies from a single frequency source, namely a quartz crystal oscilla- tor. this architecture is relatively easy to implement, especially if the feedback divider is only required to provide integer division factors. the drawback to the architecture shown in figure 1 is that the output frequency must be the same as or greater than f ref . to resolve this restriction, simply place a second programmable frequency divider at the output, as shown in figure 2 . with the additional divider the output frequency is given by f o = ( n/p ) f ref where p is the output frequency divider value. the architecture shown in figure 2 allows for rational f out /f ref ratios (that is, one integer divided by another). furthermore, for p > n, f out is less than f ref , which overcomes the aforemen- tioned drawback. note that in the previous architecture ( figure 1 ) there is a necessary harmonic relationship between f out and f ref because n is an integer. an unintentional benefit of the new architecture ( figure 2 ) is the elimination of this harmonic restriction. the same result is possible by placing the second divider at the output of the crystal oscillator instead of at the output of the pll. such an arrangement, however, means that the pll design must accommodate a range of input frequencies rather than the single crystal oscillator frequency. the architecture of figure 2 satisfies any application for which the ratio, n/p, meets the required output/input frequency ratio. the amount of flexibility provided by this architecture depends on the range of n and p, that is, the larger the range of n and p, the more flexible the solution. there is a practical limit, how- ever, to the range of n because the range of n determines the required frequency range of the voltage controlled oscillator (vco). the wider the vco range, the more difficult it is to design the vco without sacrificing performance. phase detector loop filter voltage controlled oscillator feedback divider (n) oscillator f ref f out = (n/p) f ref quartz crystal pll 07918-002 output divider (p) figure 2. pll-based frequency up converter with output divider
AN-0988 application note rev. 0 | page 4 of 8 the ad9552 architecture the ad9552 incorporates the basic architecture of figure 2 , but has a feedback divider capable of fractional divide values. a simplified block diagram of the ad9552 appears in figure 3 . the ad9552 offers two programming methods. one is via a serial communication port that provides full control of the device settings. the other is via configuration selection pins that allow the user to select one of a predefined set of common network clock frequencies simply by pin strapping the device (potentially eliminating the need for serial commu- nication). the ad9552 has nine configuration pins partitioned into a group of three (pin a0 to pin a2) and a group of six (pin y0 to pin y5). the a pins select 1 of 8 predefined reference frequencies (see table 1 ), while the y pins select 1 of 64 output frequencies (see table 2 ). the configuration pins automatically set the appropriate internal divider values for generating the frequency at out1, as indicated in table 2 . pin-selected divider values register bank serial port controller - modulator n, f, m, p 0 , p 1 3350mhz to 4050mhz pfd/ charge pump vco 2 detector dcxo (n + f/m) p 0 p 1 4to11 1to 63 1to 63 p 2 out 1 out 2 loop filter quartz crystal resonator ref configuration selection pins spi port 07918-003 figure 3. the ad9552 crystal oscill ator and frequency up-converter table 1. pin strapped reference frequency a2 a1 a0 reference frequency (mhz) 0 0 0 10.00 0 0 1 12.00 0 1 0 12.80 0 1 1 16.00 1 0 0 19.20 1 0 1 19.44 1 1 0 20.00 1 1 1 26.00
application note AN-0988 rev. 0 | page 5 of 8 table 2. pin strapped output frequency y5 y4 y3 y2 y1 y0 output (mhz) y5 y4 y3 y2 y1 y0 output (mhz) 0 0 0 0 0 0 51.84 1 0 0 0 0 0 569.1964 0 0 0 0 0 1 54 1 0 0 0 0 1 622.08 0 0 0 0 1 0 60 1 0 0 0 1 0 624.7048 0 0 0 0 1 1 61.44 1 0 0 0 1 1 625 0 0 0 1 0 0 62.5 1 0 0 1 0 0 622.08(239/237) 0 0 0 1 0 1 66.666 1 0 0 1 0 1 629.9878 0 0 0 1 1 0 74.17582 1 0 0 1 1 0 640 0 0 0 1 1 1 74.25 1 0 0 1 1 1 641.52 0 0 1 0 0 0 77.76 1 0 1 0 0 0 625(66/64) 0 0 1 0 0 1 98.304 1 0 1 0 0 1 657.421875 0 0 1 0 1 0 100 1 0 1 0 1 0 657.421875(239/238) 0 0 1 0 1 1 106.25 1 0 1 0 1 1 622.08(15/14) 0 0 1 1 0 0 120 1 0 1 1 0 0 669.1281 0 0 1 1 0 1 125 1 0 1 1 0 1 622.08(255/237) 0 0 1 1 1 0 133 1 0 1 1 1 0 625(15/14) 0 0 1 1 1 1 155.52 1 0 1 1 1 1 670.8386 0 1 0 0 0 0 156.25 1 1 0 0 0 0 622.08(255/236) 0 1 0 0 0 1 159.375 1 1 0 0 0 1 625(66/64)(15/14) 0 1 0 0 1 0 161.1328125 1 1 0 0 1 0 625(255/237)(66/64) 0 1 0 0 1 1 10518.75/64 1 1 0 0 1 1 693.75 0 1 0 1 0 0 155.52(15/14) 1 1 0 1 0 0 622.08(253/226) 0 1 0 1 0 1 155.52(255/237) 1 1 0 1 0 1 657.421875(255/238) 0 1 0 1 1 0 167.6616 1 1 0 1 1 0 657.421875(255/237) 0 1 0 1 1 1 177.7371 1 1 0 1 1 1 716.5372 0 1 1 0 0 0 245.76 1 1 1 0 0 0 718.75 0 1 1 0 0 1 250 1 1 1 0 0 1 719.7344 0 1 1 0 1 0 311.04 1 1 1 0 1 0 748.0709 0 1 1 0 1 1 320 1 1 1 0 1 1 750 0 1 1 1 0 0 400 1 1 1 1 0 0 777.6 0 1 1 1 0 1 433.925 1 1 1 1 0 1 779.5686 0 1 1 1 1 0 531.25 1 1 1 1 1 0 781.25 0 1 1 1 1 1 537.6 1 1 1 1 1 1 625(10/8)(66/64) even though the context of this application note is the use of a crystal resonator, the ad9552 also provides an alternate input source. the user can connect a single-ended cmos clock signal directly to the ref input pin of the ad9552 instead of using a crystal resonator. the ad9552 offers two output clock signals, out 1 and out 2 . out 1 is the primary output. out 2 is an auxiliary output that is programmable as an integer submultiple of the frequency at out 1 or as a copy of the frequency at the input to the phase- frequency detector (pfd) of the pll. the feedback divider of the ad9552 provides fractional division, but not to the exclusion of integer division. fractional division offers a significant amount of flexibility because the frequency scale factor takes the form n + f/m (where f/m < 1), instead of simply n as in figure 1 . the benefit of fractional division is that it yields a much wider selection of vco output frequencies (within the bandwidth of the vco) for a given reference frequency. the reason is that the ratio, f vco /f ref , must be an integer (n) for an integer-only pll, but can be a fractional value (n + f/m) for a fractional pll, which allows for a much larger set of valid frequency ratios. for example, suppose the vco range is 800 mhz to 1000 mhz and that f ref is 25 mhz. for an integer-only pll, the only possible vco output frequencies are 800 mhz to 1000 mhz in 25 mhz steps (corresponding to n values 32 to 40). conversely, a fractional pll supports any output frequency between 800 mhz and 1000 mhz as long as the fraction, f/m, has the necessary resolution. in the case of the ad9552, fractional resolution is limited to 20 bits for both f and m, which yields a resolution of 1/1,048,575. the user can program the 20-bit values for both f and m, allowing for a very large set of possible output frequencies.
AN-0988 application note rev. 0 | page 6 of 8 the fractional feedback divider of the ad9552, along with its output dividers (p 0 and p 1 ), produces a primary output frequency (f out1 ) given by f out1 = [(n + f/m )/( p 0 p 1 )] f pfd the secondary output frequency (f out2 ) of the ad9552 is f out2 = f out1 /p 2 or f out2 = f pfd depending on the selection of the signal source for out 2 . in the above equations, f pfd = f ref or f pfd = 2 f ref , depending on the selection of the optional 2 frequency multiplier. for fractional frequency division, typically the feedback divider assumes one integer value most of the time (q, for example), but periodically changes to q + 1 in such a way that the average divide ratio is the desired fractional value. the word, periodi- cally , is significant because it implies undesirable spurious artifacts in the output spectrum. to help mitigate the spurious artifacts that are normally associated with a fractional divider, the ad9552 uses a sigma-delta modulator (sdm) with a built- in pseudorandom binary sequence (prbs) generator to spread out the spurious energy. the combination of an sdm and prbs generator in the feedback divider provides sufficient spurious suppression to satisfy the specifications of many network clock applications. even though the ad9552 generates some spurious artifacts, thus limiting its usefulness as a general-purpose crystal oscilla- tor replacement, it is still well suited for the network clocking space. the reason is that the sdm moves the spurious energy far enough out of band to allow for relatively easy filtering. in fact, figure 4 and figure 5 show actual phase noise measure- ments of the ad9552 pin strapped to yield a 625 mhz output using a 26 mhz crystal resonator. the phase noise plot shown in figure 4 represents the unfiltered output of the ad9552 and demonstrates the raw performance of the device. note the spurious components between 1 mhz and 100 mhz with magnitudes ranging from about ?60 dbc to ?90 dbc. the resulting rms jitter in the sonet oc-192 band (50 khz to 80 mhz) is 0.74 ps. on the other hand, exclusion of the spurious artifacts (see figure 5 ) yields 0.51 ps of rms jitter. although not shown, measurements in the sonet oc-3 band (12 khz to 20 mhz) indicate 0.65 ps of rms jitter, either with or without the inclusion of the spurious artifacts in the measurement. for this particular application (synthesizing a 625 mhz output signal using a 26 mhz crystal), comparison of the rms jitter values, both with and without the spurious content in both the oc-3 and oc-192 bands, indicates that the spurs appearing in the 1 mhz to 10 mhz range have no significant impact on rms jitter performance. the ad9552 suppresses the spurs in the 1 mhz to 10 mhz range to the point of having no adverse affect on the rms jitter performance.
application note AN-0988 rev. 0 | page 7 of 8 rms jitter: 736.208 fsec 07918-004 figure 4. ad9552 phase noise measurement
AN-0988 application note rev. 0 | page 8 of 8 07918-005 rms jitter: 506.501 fsec figure 5. ad9552 phase noise excluding spurious artifacts conclusion the measurement results for this particular application (625 mhz out using a 26 mhz crystal) indicate that the ad9552 meets a 0.65 ps rms jitter requirement in the oc-3 band without the need for additional filtering of the output signal. on the other hand, it should be possible to achieve similar rms jitter performance (~0.6 ps) in the oc-192 band by using an external filter to suppress the spurs beyond the 1 mhz range. for example, one might use a saw filter centered at 625 mhz with a 2 mhz bandwidth. applications using a different output/input frequency ratio have a different set of spurious artifacts. thus, it is wise to analyze the spurious content of each output/input frequency ratio in an application to determine if postfiltering is necessary. if external filtering is necessary, then the appropriate filter parameters (such as bandwidth, stop-band attenuation, and insertion loss) must be determined to generate the desired jitter performance. although the ad9552 is not the only solution for network clocking applications, its flexibility, low cost, high reliability, and ease of use are significant advantages over other solutions. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. an07918-0-7 /09(0)
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